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LIN D O C #: 1660
LX1660/1661
A DVANCED PWM CONTROLLER
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DESCRIPTION The LX1660 and LX1661 Are Monolithic Switching Regulator Controller ICs designed to provide low-cost, highperformance adjustable power supply for microprocessors and other applications requiring a fast transient response and a high degree of accuracy. They provide an adjustable synchronous Pulse Width Modulator output suitable for a power supply for Pentium(R) or other microprocessors. Synchronous Rectifier Driver For CPU Core. The devices can drive dual MOSFETs resulting in typical efficiencies of 85 - 90%, even with loads in excess of 10A. Synchronous shutdown results in increased efficiency in light load applications. Short-Cir cuit Current Limiting Without Expensive Current Sense Resistors. The current sensing mechanism can use a PCB trace resistance or the parasitic resistance of the main inductor. For applications requiring a high degree of accuracy, a conventional sense resistor can be used. Hiccup Mode Fault Protection. The hiccup mode is programmable and with pulse-by-pulse current limiting will help protect the power supply system and load in the even of a short circuit. Ultra-Fast Transient Response Reduces System Cost. The fixed frequency modulated off-time architecture results in the fastest transient response for a given inductor. Adaptive voltage positioning (LX1661 only) requires fewer low-ESR capacitors to meet stringent transient overand under-shoot specifications.
K E Y F E AT U R E S
s Designed To Drive A Synchronous Rectifier Stage -- Can Also Be Used In NonSynchronous Applications s Soft-Start Capability s Hiccup-Mode Fault Protection s No Current-Sense Resistor Required For Current Limiting s Modulated Constant Off-Time Control Mechanism For Fast Transient Response And Simple System Design s 2V, 0.5% Internal Voltage Reference Brought Out
A P P L I C AT I O N S
s s s s s Pentium Processor Supplies AMD-K6TM Supplies Cyrix(R) 6x86TM Supplies Voltage Regulator Modules General Purpose DC:DC Supplies
IMPORTANT: For the most current data, consult LinFinity's web site: http://www.linfinity.com.
PRODUCT HIGHLIGHT
LX1661 IN SOCKET 7 PROCESSOR SUPPLY APPLICATION
OUTEN
12V
VIN 5V
C2
C7
R14, 1% See Table 5 R15 2.0k 1% R16 10k C4 390pF
Q1 IRL3103
16V, 1000F Sanyo MV-GX or equivalent
VOUT
U1 LX1661
1 2 3 4 5 6 7 8
EN OTADJ SGND VREF INV NINV HICCUP CT 16-pin SOIC
VC1 TDRV PGND BDRV VCC SYNCEN CS+ CS-
16 15 14 13 12 11 10 9
C9 1F
L1 5H Toroid D1
R1, 5m
C5 C6
16V, 1000F Sanyo MV-GX or equivalent
R5, 1k C1 390pF
C3 0.1F
C8 390pF
R6, 1k
PA C K A G E O R D E R I N F O R M AT I O N TA (C) 0 to 70
N Plastic DIP 16-pin
LX166xCN
D Plastic SOIC 16-pin
LX166xCD
Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. LX166xCDT)
Copyright (c) 1998 Rev. 1.1 7/98
LINFINITY MICROELECTRONICS INC.
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841, 714-898-8121, FAX: 714-893-2570
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PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET PACKAGE PIN OUTS
EN OTADJ SGND VREF INV NINV/SS HICCUP CT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
A B S O L U T E M A X I M U M R AT I N G S
(Note 1)
Supply Voltage ............................................................................................................. 25V Output Peak Current Source (500ns) ......................................................................... 1.5A Output Peak Current Sink (500ns) ............................................................................. 1.5A Analog Inputs ................................................................................................... -0.3 to +6V Power Dissipation at TA = 25C N Package ............................................................................................................... 1.5W D Package ........................................................................................................... 830mW Operating Junction Temperature Plastic (N, D Packages) ......................................................................................... 150C Storage Temperature Range .................................................................... -65C to +150C Lead Temperature (Soldering, 10 Seconds) ............................................................. 300C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Pin numbers refer to DIL packages only.
VC1 TDRV PGND BDRV VCC SYNCEN CS+ CS-
N PACKAGE (Top View)
T H E R MAL DATA
N PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA D PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA 120C/W Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow 65C/W
EN OTADJ SGND VREF INV NINV/SS HICCUP CT
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VC1 TDRV PGND BDRV VCC SYNCEN CS+ CS-
D PACKAGE (Top View)
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Copyright (c) 1998 Rev. 1.1 7/98
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, 10.8 < VCC < 13.2, 0C TA 85C. Test conditions: VCC = 12V, T = 25C.)
Parameter Reference Section
Initial Output Voltage Load Regulation Short Circuit Current ISH
Symbol
Test Conditions
LX1660 LX1661 Units Min. Typ. Max. Min. Typ. Max.
1.98 2 2 24 2.02 1.98 2 2 24 2.02 V mV mA S S % A A V V V nS V A mV nS V A mV nS nSec nSec V A V V mA V V A A V mA A mS/F %
VCC = 12V, I L = 100A VCC = 12V, IL = 10A to 5mA VREF = 1.96V OT OTADJ = 1.8V, CT = 390pF OTADJ = 3.5V, CT = 390pF OTADJ = 1.8V to 3.5V VNINV = 1.8V, V CT = 1.5V VNINV = 3.5V, V CT = 1.75V OTADJ = 1.8V OTADJ = 3.5V 10% Overdrive (Voltage at OTADJ Pin) VFB = VSET 10% Overdrive SYCEN IB VCLP 1.8V < VCS+ = VCS < 3.5V Initial Accuracy 10% Overdrive VCL = V C2 = 12V, CL = 3000pF VCL = V C2 = 12V, CL = 3000pF VCC = VC = 0, IPULL UP = 2mA tPULSE = 500ns
Timing Section
Off Time Initial Off Time Temp Stability Discharging Current Ramp Peak Ramp Peak-Valley Ramp Valley Delay to Output Turn Off Threshold 2 1 2 180 210 240 180 180 210 240 180 2 0.8 0.9 1.0 0.8 0.475 0.5 0.525 0.475 100 0.6 0.9 1.2 0.6 0.1 2 150 0.5 0.7 0.1 90 150 70 70 1 1.0 9.85 10.15 0.31 2 3 0.2 1.3 1.4 -0.5 0.5 0.14 0.16 10.45 9.85 10.15 0.31 2 3 0.6 0.2 1.5 1.3 1.4 -1 -0.5 1 0.5 0.18 0.14 0.16 1.0 36 2 1 2 210 240 210 240 2 0.9 1.0 0.5 0.525 100 0.9 1.2 0.1 42 150 0.7 0.1 90 150 70 70 1 1.0 10.45 1.0 48
IDIS VP VRPP
VOFF IB VIO
Error Comparator Section
Input Bias Current Input Offset Voltage EC Delay to Output
Synchronous Control Section
Synchronous Enable Threshold 0.9 1 100 0.5 0.9 1 100
Current Sense Section
Input Bias Current Pulse By Pulse CL CS Delay to Output 80 80
Output Drivers Section
Output Rise Time Output Fall Time Output Pull Down Peak Current TR TF VPD IPK VST VHYST ISD VOL VEN IEN
UVLO and S.S. Section
Start-Up Threshold Hysteresis S.S. Sink Current S.S. Sat Voltage Enable Shutdown Threshold Enable Bias Current Enable Hysteresis
VCL = 10.1V VCL = 9V, ISD = 20A IEN (Low), VEN = 0V IEN (High), V EN = 2V
0.6 1.5 -1 1 0.18
Supply Current Section
Dynamic Operating Current Start-Up Current ICD I ST VCC = V C = 12V, Out Freq = 200kHz, CL = 0 VCL = 10V (CHICCUP = 0.1F typ.) 25 500 1000 100 10 25 500 1000 100 10
Hiccup Section
Hiccup Factor "ON" Time Hiccup Duty Cycle
Copyright (c) 1998 Rev. 1.1 7/98
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PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
BLOCK DIAGRAM
VCC EN 1 ENABLE 2V OUT UVLO 10.6/10.1 2V REF PWM LATCH S 1.4V EN INTERNAL VCC Q
15 TDRV 16 VC1
VREG 5V
R DOM
R
Q
14 PGND
OTADJ 2 BREAK BEFORE MAKE
SGND 3
13 BDRV
VREF 4
40mV (1661 only)
VREG GOOD ERROR COMP
12 VCC
INV 5
NINV/SS 6
OTADJ VPEAK = 2V VVAL = 1V UPGRADE OFFTIME CONTROL
SYNC EN COMP
11 SYNCEN
HICCUP 7
CT 8 0.7V VCC 10 I HICCUP S Q I 1.5V
IMAX
10 CS+
9 CS-
90mV
R
Q
HICCUP LATCH
FIGURE 1 -- Block Diagram
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Copyright (c) 1998 Rev. 1.1 7/98
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
P
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D
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HEET
FUNCTIONAL PIN DESCRIPTION
Pin
EN OT ADJ
#
1 2
Description
A low voltage at this pin puts the IC in sleep-mode. The purpose of this pin is to allow modulation of the OFF-time relative to the reference voltage. The OFF-time is inversely proportional to the reference voltage. The inverting input of the upgrade voltage comparator is also connected to this pin, when the voltage at this pin is below 0.7V, the controller shuts down. This pin is the signal ground of the IC. 2V reference. This pin is the inverting input of the error comparator. This pin is the non-inverting input of the error comparator (LX1661 only: 40mV offset between this pin and error comparator). This pin is pulled low during sleep-mode to allow soft-start function during start up. A hiccup-mode capacitor connected to this pin adjusts duty cycle. The OFF-time is programmed by connecting a capacitor from this pin to ground. This is the inverting input of the pulse-by-pulse current comparator. This is the non-inverting input of the pulse-by-pulse current comparator. This pin enables the synchronous (bottom) driver. A high voltage at this pin disables the synchronous driver. This is the IC supply voltage as well as the supply to the bottom MOSFET. This is the gate drive to the bottom MOSFET This is a separate ground for the top and bottom MOSFET. This is the gate drive to the top MOSFET. This pin is a separate power supply input for the top drive.
SGND VREF INV NINV/SS
3 4 5 6 7 8 9 10 11 12 13 14 15 16
HICCUP CT CSCS+ SYNCEN VCC BDRV PGND TDRV VC1
Copyright (c) 1998 Rev. 1.1 7/98
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PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
T H E O R Y O F O P E R AT I O N IC OPERATION Referring to the block diagram and typical application circuit, the output turns ON the top MOSFET, allowing the inductor current to increase. At the error comparator threshold, the PWM latch is reset, the top MOSFET turns OFF and the synchronous MOSFET turns ON. The OFF-time capacitor CT is now allowed to discharge. At the valley voltage, the synchronous MOSFET turns OFF and the top MOSFET turns on. A special break-before-make circuit prevents simultaneous conduction of the two MOSFETs. To minimize frequency variation with varying output voltage, the OFF-time is modulated as a function of the voltage at the OTADJ pin. The OTADJ pin is also being monitored for a minimum voltage of 0.7V. Below 0.7V the controller will shut down. A low voltage at the EN pin or the OTADJ pin will put the controller in a sleep mode. During the sleep mode the NINV pin is pulled low. This discharges the external bypass capacitor on this pin and allows for a soft-start.
s The peak voltage at the VFB pin is 40mV higher than the set voltage and its average is the peak voltage minus the ripple voltage at VFB pin. s The output voltage is the voltage at the VFB pin minus the voltage drop across the current sensing resistor (I * RSENSE). s At light loads, the voltage drop across the sensing resistor is small; hence, the output voltage is approximately the voltage at the VFB pin (approximately 40mV higher than the nominal set-point voltage, VSET). s At heavy loads, larger current flows in the sense resistor, therefore, the voltage drop is higher and the output voltage is lower.
This adaptive positioning of the output voltage as the load changes allows a greater output voltage excursion during a fast step-load transient and requires fewer output capacitors to meet the transient-response specification.
+VCC C Q1 +V C VFB (LX1661) RS COUT VFB (LX1660) LOAD
Regulation LX1660 Only: The INV pin is connected to the negative side of the sense resistor (i.e. the actual voltage supplied to the load) -- See Figure 2. The LX1660 will achieve a high DC setpoint accuracy, since it regulates at the load, but it will have greater transient voltage over- and under-shoots than the LX1661.
LX1661 Only: The INV pin is connected to the positive side of the sense resistor (between the inductor and the sense resistor) -- See Figure 2. The LX1661 has a 40mV offset to the NINV pin to enhance transient response, as shown in Figure 3 below.
ENABLE VFB VCONTROL
EN INV NINV HICCUP CT CS-
A TDRV BDRV VREF CS+ B Q2
L
CS+ 2V
CS-
CHICCUP
CT
C R R
To RS
Figure 2 -- LX1660 / 1661 General Circuit Configuration
Steady-state output voltage at low current ~40mV above nominal set-point Load current
Nominal set-point voltage, VSET
Output voltage (VOUT)
Voltage drop (mainly) due to current change and ESR of capacitors, V = I * ESR (Effects of ESL ignored in this analysis)
Steady-state voltage at high current is approximately VSET + 40mV - I * RSENSE
Figure 3 -- Adaptive Voltage Positioning
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Copyright (c) 1998 Rev. 1.1 7/98
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
T H E O R Y O F O P E R A T I O N (continued) ERROR VOLTAGE COMPARATOR The error voltage comparator compares the feedback voltage at the positive side of the sense resistor to the set voltage (set voltage plus 40mV in LX1661). An external filter is recommended for highfrequency noise. CURRENT LIMIT AND HICCUP SECTIONS Current limiting is performed by sensing the inductor current across the sense resistor. Exceeding this threshold turns the output drive OFF and latches it OFF until the PWM latch set input goes high again. To reduce stress on the external MOSFET and SCR during output shorts or heavy-load conditions, a hiccup circuit is incorporated, which provides 10% duty cycle. The hiccup time is programmed via a capacitor at the HICCUP pin. A low voltage at this pin disables the hiccup function. OFF TIME CONTROL TIMING SECTION The timing capacitor CT allows programming of the OFF-time. The timing capacitor is quickly charged during the ON time of the top MOSFET and allowed to discharge when the top MOSFET is OFF. UNDER VOLTAGE LOCKOUT AND SHUTDOWN SECTION The purpose of the UVLO is to keep the output drive off and to maintain low quiescent current until the input voltage reaches the start-up threshold. At voltages below the start-up voltage, the UVLO comparator disables the internal biasing, and turns off the output drives. The NINV pin is pulled low. SYNCHRONOUS CONTROL SECTION The synchronous control section incorporates a unique breakbefore-make function to ensure that the primary switch and the synchronous switch are not turned on at the same time. Approximately 100 nanoseconds of deadtime is provided by the breakbefore-make circuitry to protect the MOSFET switches. OFF TIME CONTROL TIMING SECTION (continued) In order to minimize frequency variations while providing different supply voltages, the discharge current is modulated by the voltage at the OTADJ pin. The OFF-time is inversely proportional to the OTADJ voltage. If the OT ADJ voltage drops below 0.7V, the IC shuts down into a low quiescent current mode.
A P P L I C AT I O N I N F O R M AT I O N
12V
See Note 1 C2 x 3 6.3V, 1500F Sanyo MV-GX or equivalent Fuse (F1) is optional
VIN 5V
F1
V OUT = VREF * (1 + R14/R15) (VREF = 2.0V)
Q1 IRL3103 C9 1F L1
VOUT 3.3V
R14 1.3k (See Table 5) R15 2.0k R16 10k R3, 1k C7 0.1F
LX1660
R4 1k C4 390pF
1 2 3 4 5 6 7 8
R1, 5m
See Note 2
EN OTADJ SGND VREF INV NINV HICCUP CT 16-pin SOIC
VC1 TDRV PGND BDRV VCC SYNCEN CS+ CS-
16 15 14 13 12 11 10 9
5H Toroid D1 See Note 4
C5 x 6
6.3V, 1500F Sanyo MV-GX or equivalent
C3 0.1F
R5, 1k C1 390pF R6, 1k
C8 680pF
See Note 3
Notes 1. The number of capacitors within this bank may be reduced for cost savings at a penalty of increased ripple on the input bus. 2. The number of capacitors in the output filter bank may be reduced by two in a typical application; more may be removed for systems with lesser transient requirements. 3. If pulse-by-pulse current limiting is desired, remove C7 and short LX1660 pin 7 to ground. 4. D1 is Motorola MBR1035 for 10A capability; downsize as per required current.
Figure 4 -- LX1660 Controller Used In A Typical Stand-Alone High-Current 5V To 3.3V Regulator Application
Copyright (c) 1998 Rev. 1.1 7/98
7
PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
A P P L I C AT I O N I N F O R M AT I O N
See Note 1
D1 1N4148 D2 1N4148 F1 C20 0.1F R13 10 JP4 JP3 16A 32V C2 1500F 6.3V Q1 IRL3103 C11 1500F 6.3V JP1 JP2 12VIN 5VIN
See Note 1
R4 1K C10 0.1F C4 390F
1 2 3 4 5 6 7 8
VRM CONTROLLER
EN OTADJ SGND VVREF INV NINV/SS HICCUP CT VC1 TDRV PGND BDRV VCC SYNCEN CS+
16 15 14 13 12 11 10
C9 1F R7 10 C19 0.1F
See Note 1
L1 TOROID 5H Q2 IRL3103 R5 1K R6 1K Q3 2N6504 R1 5m C5 C12 C13
1500F 6.3V
LX1670
1 2 3 4 5 6 7
PWRGD OUTEN
VIDO VSENSE PGOOD OVOUT ENABLE BLKEN GND
VCC D4B D4 D3 D2 D1 D0
14 13 12 11 10 9 8
R2 10K VID4 VID3 VID2 VID1 VID0
R3 1K C7 0.1F
R8 10
CS- 9
C3 0.1F
C8 680pF
LX1661
C1 390pF
SUPPLY OUTPUT CLAMP
Note 1. Setup shown is for 5V application. For 12V input change the following: - Close JP1 and JP4
- Open JP2 and JP3 - For C2 and C11, use 16V/850F capacitors instead - Inductor L1 = 10H
Figure 5 -- Full Featured Voltage Regulator Using LX1661 Controller And LX1670 Programmable Reference / DAC Chip For Pentium Pro Processor Or Pentium II Processor Applications
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Copyright (c) 1998 Rev. 1.1 7/98
1500F 6.3V
1500F 6.3V
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
A P P L I C AT I O N I N F O R M AT I O N
OUTEN 12V VIN 5V
C2
C7
16V, 1000F Sanyo MV-GX or equivalent
VOUT
U2
8
1/2 LM358
3
R4 1k
Q1 IRL3103
U1 LX1661
1 2 3
4
2
EN OTADJ SGND VREF INV NINV HICCUP CT 16-pin SOIC
VC1 TDRV PGND BDRV VCC SYNCEN CS+ CS-
16 15 14 13 12 11 10 9
C9 1F
L1 5H Toroid D1
R1, 5m
C5 C6
R24 Jumper VID0 VID1 VID2 VID3 1k, 1% R23, 20k 1% R22, 10k 1% R21, 5k 1% R20, 2.5k 1%
R16 10k
4
C4 390pF
5 6 7
16V, 1000F Sanyo MV-GX or equivalent
R5, 1k C1 390pF
C3 0.1F C8 680pF
8
R6, 1k
Figure 6 -- Low Cost Programmable Power Supply For Socket 7 Processors
TABLE 1 - Voltage Identification Code (VID)
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Setting The Output Voltage The output voltage is set by means of a 4-bit digital VID code. For processors that do not have VID coded into the package, the VID code can be set by means of a jumper or DIP switch. For low or `0' signal, connect the VID pin to ground (DIP switch ON). For high or `1', leave open (DIP switch OFF).
Note: Costs are estimates only. Check with suppliers for exact quotation.
Copyright (c) 1998 Rev. 1.1 7/98
9
PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
USING THE LX1660/61 DEVICES The LX1660/61 devices are very easy to design with, requiring only a few simple calculations to implement a given design. The following procedures and considerations should provide effective operation for virtually all applications. Refer to the Application Information section for component reference designators. SELECTING BETWEEN THE LX1660 AND THE LX1661 In order to provide maximum user versatility, the Advanced PWM Controller is offered in two versions: the LX1660 and the LX1661. The LX1661 has a 40mV offset built-in which compensates for the current sense resistor voltage drop. This allows optimal transient response for high-speed systems, such as Pentium Pro processor power supplies. Overall system design could be more economical with the LX1661, since output capacitance requirements could be eased. The LX1660 provides a very accurate DC set-point, since the 40mV offset is not included in the device. This device is good for critical DC applications, such as core power in slower microprocessors and related systems. See "Theory Of Operation" section earlier in this data sheet. OUTPUT INDUCTOR The output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. The peak-to-peak output voltage ripple is: VRIPPLE = ESR * IRIPPLE where, IRIPPLE = INPUT INDUCTOR In order to supply faster transient load changes, a smaller output inductor is needed. However, reducing the size of the output inductor will result in a higher ripple voltage on the input supply. This noise on the 5V rail can affect other system components, such as graphic cards. In this case, it is recommended that a 1 - 1.5H inductor is used on the input to the regulator, to filter the ripple on the 5V supply. Ensure that this inductor has the same current rating as the output inductor. OUTPUT CAPACITOR The output capacitor is sized to meet ripple and transient performance specifications. Effective Series Resistance (ESR) is a critical parameter. When a step load current occurs, the output voltage will have a step that equals the product of the ESR and the current step, I. In an advance microprocessor power supply, the output capacitor is usually selected for ESR instead of capacitance or RMS current capability. A capacitor that satisfies the ESR requirement usually has a larger capacitance and current capability than strictly needed. The allowed ESR can be found by: ESR * (IRIPPLE + I) < VEX where IRIPPLE is the inductor ripple current, I is the maximum load current step change, and VEX is the allowed output voltage excursion in the transient. Adaptive voltage positioning increases the value of VEX, allowing a higher ESR value and reducing the cost of the output capacitor. Typically, the positioning voltage is 40mV, using the LX1661, and the transient tolerance is 100mV, resulting in a VEX of 140mV (See Figure 3). The LX1660 does not have the positioning voltage offset, so VEX is 100mV maximum. Electrolytic capacitors can be used for the output capacitor, but are less stable with age than tantalum capacitors. As they age, their ESR degrades, reducing the system performance and increasing the risk of failure. It is recommended that multiple parallel capacitors be used, so that, as ESR increases with age, overall performance will still meet the processor's requirements. There is frequently strong pressure to use the least expensive components possible, however, this could lead to degraded longterm reliability, especially in the case of filter capacitors. Linfinity's demonstration boards use Sanyo MV-GX filter capacitors, which are aluminum electrolytic, and have demonstrated reliability. The Oscon series from Sanyo generally provides the very best performance in terms of long term ESR stability and general reliability, but at a substantial cost penalty. The MV-GX series provides excellent ESR performance at a reasonable cost. Beware of off-brand, very low-cost filter capacitors, which have been shown to degrade in both ESR and general electrolytic characteristics over time.
VIN - VOUT VOUT * fSW * L VIN
IRIPPLE is the inductor ripple current, L is the output inductor value and ESR is the Effective Series Resistance of the output capacitor. IRIPPLE should typically be in the range of 20% to 40% of the maximum output current. Higher inductance results in lower output voltage ripple, allowing slightly higher ESR to satisfy the transient specification. Higher inductance also slows the inductor current slew rate in response to the load-current step change, I, resulting in more output-capacitor voltage droop. The inductorcurrent slew rates at rise and fall edges are: TRISE = L * I / (VIN - VOUT ) and, TFALL = L * I / VOUT When using electrolytic capacitors, the capacitor voltage droop is usually negligible, due to the large capacitance.
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Copyright (c) 1998 Rev. 1.1 7/98
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
USING THE LX1660/61 DEVICES INPUT CAPACITOR The input capacitor and the input inductor are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5V rail. In addition, the input capacitor provides local de-coupling of the buck converter. The capacitor should be rated to handle the RMS current requirement. The RMS current is: IRMS = IL d(1-d) where IL is the inductor current and d is the duty cycle. The maximum value, when d = 50%, IRMS = 0.5IL . For 5V input and output in the range of 2 to 3V, the required RMS current is very close to 0.5IL . A high-frequency (ceramic) capacitor should be placed across the drain of the top MOSFET and the source of the bottom one to avoid ringing due to the parasitic inductor being switched ON and OFF. See capacitor C7 in the Product Highlight on the first page of this data sheet. TIMING CAPACITOR SELECTION The frequency of operation of the LX1660 / 1661 is a function of the duty cycle and OFF-time. The OFF-time is proportional to the timing capacitor (connected to Pin 8, CT ), and is modulated to minimize frequency variations with duty cycle. The frequency is constant, during steady-state operation, due to the modulation of the OFF-time. The timing capacitor (CT) should be selected using the following equation: CT = CURRENT LIMIT
(continued)
parasitic resistance of the inductor. One should include an RC filter at the CS+ and CS- inputs, as shown in the Application Information section, to eliminate jitter and noise. For most applications, the resistors R5, R6 can be set at 1k, and C1 can be in the 300-500pF range as a starting point. If a fine trim or adjustment of the current trip level is required, C1 may be shunted by a resistor. C1 will introduce a small delay into the current limit trip point, which effectively raises the threshold.
Sense Resistor The current sense resistor (R1) is selected according to the formula: R1 = VTRIP / ITRIP
Where VTRIP is the current sense comparator threshold (100mV) and ITRIP is the desired current limit. Typical choices are shown below. TABLE 2 - Current Sense Resistor Selection Guide
Load
Pentium-Class Processor (<10A) Pentium II Class (>10A)
Sense Resistor Value
5m 2.5m
(1 - VOUT / V IN ) * IDIS fS (1.52 - 0.29 * VOUT )
where IDIS is fixed at 200A and f S is the switching frequency (recommended to be around 200kHz for optimal operation and component selection). When using a 5V input voltage, the switching frequency (f S) can be approximated as follows: CT = 0.621 *
A smaller sense resistor will result in lower heat dissipation (IR) and also a smaller output voltage droop at higher currents. There are several alternative types of sense resistor. The surface-mount metal "staple" form of resistor has the advantage of exposure to free air to dissipate heat and its value can be controlled very tightly. Its main drawback, however, is cost. An alternative is to construct the sense resistor using a copper PCB trace. Although the resistance cannot be controlled as tightly, the PCB trace is very low cost.
IDIS fS
PCB Sense Resistor A PCB sense resistor should be constructed as shown in Figure 7. By attaching directly to the large pads for the capacitor and inductor, heat is dissipated efficiently by the larger copper masses. Connect the current sense lines as shown to avoid any errors.
2.5m Sense Resistor Inductor
100mil Wide, 850mil Long 2.5mm x 22mm (2 oz/ft2 copper)
Choosing a 680pF timing capacitor will result in an operating frequency of 183kHz at VOUT = 2.8V. When a 12V power input is used, the capacitor value must be changed (the optimal timing capacitor for 12V input will be in the range of 1000 - 1500pF). CURRENT LIMIT Current limiting occurs when a sensed voltage, proportional to load current, exceeds the current-sense comparator threshold value (90mV). The current can be sensed either by using a fixed sense resistor in series with the inductor to cause a voltage drop proportional to current, or by using a resistor and capacitor in parallel with the inductor to sense the voltage drop across the
Output Capacitor Pad Sense Lines
FIGURE 7 -- Sense Resistor Construction Diagram
Copyright (c) 1998 Rev. 1.1 7/98
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PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
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D
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USING THE LX1660/61 DEVICES CURRENT LIMIT
(continued)
CURRENT LIMIT
(continued)
Recommended sense resistor sizes are given in the following table: TABLE 3 - PCB Sense Resistor Selection Guide
Copper Weight
2 oz/ft2
The dc/static tripping current Itrip,S satisfies: Itrip,S = Vtrip RL
Copper Desired Resistor Thickness Value
68m 2.5m 5m
Dimensions (w x l) mm inches
2.5 x 22 2.5 x 43 0.1 x 0.85 0.1 x 1.7
Select L/RSC S RL to have higher dynamic tripping current than the static one. The dynamic tripping current Itrip,d satisfies: Itrip,d = Vtrip L/(RSCS)
Loss-Less Current Sensing Using Resistance of Inductor Any inductor has a parasitic resistance, RL, which causes a DC voltage drop when current flows through the inductor. Figure 8 shows a sensor circuit comprising of a surface mount resistor, RS, and capacitor, CS, in parallel with the inductor, eliminating the current sense resistor.
General Guidelines for Selecting RS , CS , and RL
Vtrip RL = I trip,S and CS according to: Select: RS 10 k Ln CS n = RL RS
L
RL
Load
RS Current Sense Comparator
CS VCS RS2
The above equation has taken into account the current-dependency of the inductance. Typical values are: RL = 3m, R S = 9k, CS = 0.1F, and L is 2.5H at 0A current. In cases where RL is so large that the trip point current would be lower than the desired short-circuit current limit, a resistor (RS2) can be put in parallel with CS, as shown in Figure 8. The selection of components is as follows:
FIGURE 8 -- Current Sense Circuit The current flowing through the inductor is a triangle wave. If the sensor components are selected such that: L/RL = RS * CS The voltage across the capacitor will be equal to the current flowing through the resistor, i.e. VCS = I LR L Since VCS reflects the inductor current, by selecting the appropriate RS and CS , VCS can be made to reach the comparator voltage at the desired trip current.
RL (Required) RS2 = RL (Actual) RS2 + R S
CS =
RL (Actual)
L L RS + RS2 = * RL (Actual) RS2 * RS * (RS2 // RS)
Again, select (RS2 //RS) < 10k. C4 ERROR COMPARATOR INPUT BYPASS CAPACITOR The LX1660/61 device has a unique topology which results in extremely fast response to transient disturbances. Actual loop closure is around a comparator. A capacitor should be placed between the INV and NINV Error Comparator inputs to eliminate jitter and noise. This capacitor value should be: C = 1/2 C T , where CT is the timing capacitor. Refer to Capacitor C4 in the Application Information section. C7 HICCUP CAPACITOR SELECTION The hiccup capacitor controls two time periods; the ON time duration of 10% duty cycle mode, and the OFF-time duration before re-try. The ON:OFF-time ratios will always be 1:10 due to the current sources which charge (10I) and discharge (I) the hiccup capacitor. Select CHICCUP by using:
Design Example (Pentium II circuit, with a maximum static current of 14.2A) The gain of the sensor can be characterized as:
|T(j)|
RL L/RSCS
Duration of reduced D operation = 100ms/F
1/RSCS
RL/L
FIGURE 9 -- Sensor Gain
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Copyright (c) 1998 Rev. 1.1 7/98
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
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USING THE LX1660/61 DEVICES C7 HICCUP CAPACITOR SELECTION
(continued)
FET SELECTION
(continued)
The resulting time is the duration allowed for the 10% duty cycle drive to be applied to the bottom switch (the top switch is OFF during current limit). The OFF-time will be fixed at ten times (10x) this number, and determines the time interval the supply remains completely OFF until re-try. If the short has been removed, the supply will resume normal operation. No power cycling is necessary to reset the VRM module after a current limit event. As an example, if a 0.1F hiccup capacitor is chosen, the bottom switch drive will pulse at (approximately) a 10% duty cycle for 10mA, when current limit is reached. It will then shut OFF for 100ms, at which time a re-try cycle is attempted, which will result in either normal operation or another 10% duty cycle burst. FET SELECTION To insure reliable operation, the operating junction temperature of the FET switches must be kept below certain limits. The Intel specification states that 115C maximum junction temperature should be maintained with an ambient of 50C. This is achieved by properly derating the part, and by adequate heat sinking. One of the most critical parameters for FET selection is the RDS(ON) resistance. This parameter directly contributes to the power dissipation of the FET devices, and thus impacts heat sink design, mechanical layout, and reliability. In general, the larger the current handling capability of the FET, the lower the RDS(ON) will be, since more die area is available. TABLE 4 - FET Selection Guide
This table gives selection of suitable FETs from International Rectifier.
For the IRL3102 (13m RDS(ON)), converting 5V to 2.8V at 14A will result in typical heat dissipation of 1.48W.
Synchronous Rectification - Lower MOSFET The lower pass element can be either a MOSFET or a Schottky diode. The use of a MOSFET (synchronous rectification) will result in higher efficiency, but at higher cost than using a Schottky diode (non-synchronous). Power dissipated in the bottom MOSFET will be:
PD = I2 * RDS(ON) * [1 - Duty Cycle] = 2.24W [IRL3303 or 1.12W for the IRL3102]
Non-Synchronous Operation - Schottky Diode A typical Schottky diode, with a forward drop of 0.6V will dissipate 0.6 * 14 * [1 - 2.8/5] = 3.7W (compared to the 1.1 to 2.2W dissipated by a MOSFET under the same conditions). This power loss becomes much more significant at lower duty cycles - synchronous rectification is recommended especially when a 12Vpower input is used. The use of a dual Schottky diode in a single TO-220 package (e.g. the MBR2535) helps improve thermal dissipation.
MOSFET GATE BIAS The power MOSFETs can be biased by one of two methods: charge pump or 12V supply connected to VC1. 1) Charge Pump (Bootstrap) When 12V is supplied to the drain of the MOSFET, as in Figure 5 (option), the gate drive needs to be higher than 12V in order to turn the MOSFET on. Capacitor C20 and diodes D1 & D2 are used as a charge pump voltage doubling circuit to raise the voltage of VC1 so that the TDRV pin always provides a high enough voltage to turn on Q1. The 12V supply must always be connected to VCC to provide power for the IC itself, as well as gate drive for the bottom MOSFET. 2) 12V Supply When 5V is supplied to the drain of Q1, a 12V supply should be connected to both VCC and VC1. CURRENT SHARE APPLICATION Synchronous rectifier stages should not be paralleled unless they are locked in at the same frequency, or undesirable current sourcing/sinking could occur. If synchronization is not practical, the next best alternative is to disable the synchronous (bottom) switch. This is easily accomplished with the LX1660/61 by pulling the SYNCEN pin HIGH. In most applications, a 5 to 6% reduction in efficiency will result when the synchronous driver is disabled. A Schottky diode of the proper voltage and current ratings should be installed across the inactive FET to conduct the inductor current.
Device
IRL3803 IRL22203N IRL3103 IRL3102 IRL3303 IRL2703
RDS(ON) @ 10V (m)
6 7 14 13 26 40
ID @ TC = 100C
83 71 40 56 24 17
Max. Breakdown Voltage
30 30 30 20 30 30
All devices in TO-220 package. For surface mount devices (TO-263 / D2-Pak), add 'S' to part number, e.g. IRL3103S.
The recommended solution is to use IRL3102 for the high side and IRL3303 for the low side FET, for the best combination of cost and performance. Alternative FET's from any manufacturer could be used, provided they meet the same criteria for RDS(ON).
Heat Dissipated In Upper MOSFET The heat dissipated in the top MOSFET will be:
PD = (I2 * R DS(ON) * Duty Cycle) + (0.5 * I * V IN * t SW * fS ) where tSW is switching transition line for body diode (~100ns) and fS is the switching frequency.
Copyright (c) 1998 Rev. 1.1 7/98
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PRODUCT DATABOOK 1996/1997
LX1660/1661
ADVANCED PWM CONTROLLER
P
RODUCTION
D
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HEET
USING THE LX1660/61 DEVICES USING THE LX1660/1661 IN PROGRAMMABLE APPLICATIONS The LX1660/61 device may be used in conjunction with the LX1670 Programmable Reference to implement a high-performance, digitally-controlled switched-mode power supply suitable for Pentium Pro Processors and other advanced microprocessorbased designs. The LX1670 incorporates a 5-bit equivalent DAC, which can be programmed by the microprocessor's Voltage Identification Code (VID). The LX1670 then commands the LX1660/61 to provide the required output voltage. System protection functions such as over voltage, SCR drive, and powergood detection are embedded within the LX1670 device. See Figure 5. PROGRAMMING THE OUTPUT VOLTAGE Select the voltage divider R14 and R15 values as shown in the table below, using 1% metal film resistors: Desired Converter VOUT 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 TABLE 5 R14 Value 806 909 1.0k 1.10k 1.21k 1.30k 1.40k 1.50k R15 Value 2k 2k 2k 2k 2k 2k 2k 2k LAYOUT GUIDELINES - THERMAL DESIGN
(continued)
cases are well suited for this application, and are the preferred packages. Remember to remove any conformal coating from all exposed PC traces which are involved in heatsinking.
General Notes As always, be sure to provide local capacitive de-coupling close to the chip. Be sure use ground plane construction for all highfrequency work. Use low ESR capacitors where justified, but be alert for damping and ringing problems. High-frequency designs demand careful routing and layout, and may require several iterations to achieve desired performance levels. Power Traces To reduce power losses due to ohmic resistance, careful consideration should be given to the layout of traces that carry high currents. The main paths to consider are:
s Input power from 5V supply to drain of top MOSFET. s Trace between top MOSFET and lower MOSFET or Schottky diode. s Trace between lower MOSFET or Schottky diode and ground. s Trace between source of top MOSFET and inductor, sense resistor and load. All of these traces should be made as wide and thick as possible, in order to minimize resistance and hence power losses. It is also recommended that, whenever possible, the ground, input and output power signals should be on separate planes (PCB layers). See Figure 10 - bold traces are power traces.
If other VOUT values are needed, the divider values may be calculated as follows: VOUT = VREF (1 + R14/R15) where VREF = 2.0V. Note that resistor R4 is part of a filter element, and does not enter into the calculations. Please refer to the Application Information schematic for the reference designators and part locations. LAYOUT GUIDELINES - THERMAL DESIGN A great deal of time and effort were spent optimizing the thermal design of the demo boards. Any user who intends to implement an embedded motherboard would be well advised to carefully read and follow these guidelines. If the FET switches have been carefully selected, external heatsinking is generally not required. However, this means that copper trace on the PC board must now be used. This is a potential trouble spot; as much copper area as possible must be dedicated to heatsinking the FET switches, and the diode as well if a non-synchronous solution is used. In our VRM module, heatsink area was taken from internal ground and VCC planes which were actually split and connected with VIAS to the power device tabs. The TO-220 and TO-263
5V Input
LX166x Output
FIGURE 10 -- Power Traces
14
Copyright (c) 1998 Rev. 1.1 7/98
PRODUCT DATABOOK 1996/1997
LX1660/1661
A DVANCED PWM CONTROLLER
P
RODUCTION
D
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S
HEET
USING THE LX1660/61 DEVICES
C9 Input De-coupling (VCC) Capacitor Ensure that this 1F capacitor is placed as close to the IC as possible to minimize the effects of noise on the device. Layout Assistance Please contact Linfinity's Applications Engineers for assistance with any layout or component selection issues. A Gerber file with layout for the most popular devices is available upon request. Evaluation boards are also available upon request. Please check Linfinity's web site for further application notes.
R E L AT E D D E V I C E S
LX1662/1663 Single-Chip Programmable PWM Controller w/ 5-Bit DAC LX1664/1665 Dual Output PWM for Processor Applications LX1668 Triple Output PWM for Processor Applications LX1553 PWM for 5V - 3.3V Conversion LX1670 Programmable Reference & Voltage Monitor
Pentium is a registered trademark of Intel Corporation. Cyrix is a registered trademark and 6x86 is a trademark of Cyrix Corporation. K6 is a trademark of AMD.
PRODUCTION DATA - Information contained in this document is proprietary to Lin Finity, and is current as of publication date. This document may not be modified in any way without the express written consent of LinFinity. Product processing does not necessarily include testing of all parameters. Linfinity reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright (c) 1998 Rev. 1.1 7/98
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